ATtiny85 Atmel Corporation, ATtiny85 Datasheet - Page 149

• Manufacturer Part Number: ATtiny85
• Manufacturer: Atmel Corporation

Specifications of ATtiny85

• Flash (kbytes): 8 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.7
19.8
19.9
19.9.1
2586N–AVR–04/11
Preventing Flash Corruption
Programming Time for Flash when Using SPM
Register Description
SPMCSR – Store Program Memory Control and Status Register
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 19-1.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in
SPMCSR will return the selected data (depending on Z-pointer value) from the device signature
imprint table into the destination register. See
details.
Bit
0x37
Read/Write
Initial Value
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. Minimum and maximum programming time is per individual operation.
SPM Programming Time
Symbol
R
7
–
0
CC
, the Flash program can be corrupted because the supply voltage is
R
6
–
0
RSIG
R/W
5
0
(1)
Min Programming Time
CTPB
R/W
4
0
“Device Signature Imprint Table” on page 153
3.7 ms
RFLB
R/W
3
0
PGWRT
Table 19-1
R/W
2
0
CC
ATtiny25/45/85
reset protection circuit
PGERS
Max Programming Time
R/W
1
0
shows the typical pro-
CC
. This will pre-
4.5 ms
SPMEN
R/W
0
0
SPMCSR
149
for