PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 89

IC CONTROLLER INTERFACE 388-BGA

PEB20256E-V21

Manufacturer Part Number
PEB20256E-V21
Description
IC CONTROLLER INTERFACE 388-BGA
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20256E-V21

Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, PPP, Serial, TMA
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
200mA
Power (watts)
3W
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Circuits
-
Other names
PEB20256E-V21
PEB20256E-V21IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB20256E-V21
Manufacturer:
MAX
Quantity:
63
Part Number:
PEB20256E-V21
Manufacturer:
Infineon Technologies
Quantity:
10 000
Receive Interrupt II
CHAN
RHI
RAB
FE
HRAB
RAB, HRAB
Data Sheet
RHI
31
15
1
RAB
30
14
01
B
FE HRAB MFL RFOD CRC ILEN
29
13
Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
(Receive) Host Initiated Interrupt
The ’(Receive) Host Initiated’ interrupt vector will be issued, if bit RHI is
set in a receive descriptor and processing of this descriptor has finished.
After receiving this interrupt vector, system software can release the
descriptor, e.g. put the descriptor into a free pool.
Receive Abort
The ’Receive Abort’ interrupt vector is generated, when an incoming
data packet is aborted (more than 6 ‘1’ in case of HDLC or more than 15
‘1’ in case of PPP) or if the receiver got a receive abort command from
the system CPU.
Frame End
The ’Frame End’ interrupt Vector is generated, when one complete
frame has been received completely and has been stored in system
memory.
Hold Caused Receive Abort
The ’Hold Caused Receive Abort’ interrupt vector is generated, when the
receiver discarded the first data packet after it has found a HOLD bit in
a receive descriptor.
Silent Discard
The ’Silent Discard’ interrupt vector (bit RAB and HRAB set together)
occurs, if two or more frames have been discarded by the receiver due
to continuous inaccessibility of receive descriptor. This occurs, if receive
descriptor has HOLD bit set and receiver gets further data packets. The
interrupt vector will be generated for each packet discarded.
28
12
01
B
27
11
26
10
QUEUE(2:0)
9
24
8
89
23
0
7
22
0
21
CHAN(7:0)
Functional Description
DESID(5:0)
PEB 20256 E
PEF 20256 E
04.2001
16
0

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