PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 213
![IC CONTROLLER INTERFACE 388-BGA](/photos/6/98/69826/peb20256e-v21_sml.jpg)
PEB20256E-V21
Manufacturer Part Number
PEB20256E-V21
Description
IC CONTROLLER INTERFACE 388-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PEB20256E-V21.pdf
(232 pages)
Specifications of PEB20256E-V21
Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, PPP, Serial, TMA
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
200mA
Power (watts)
3W
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Circuits
-
Other names
PEB20256E-V21
PEB20256E-V21IN
PEB20256E-V21IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB20256E-V21
Manufacturer:
MAX
Quantity:
63
Company:
Part Number:
PEB20256E-V21
Manufacturer:
Infineon Technologies
Quantity:
10 000
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•
Figure 9-12
Table 9-9
Note: t
Data Sheet
60a
60b
61a
61b
62a
62b
63a
63b
67a
67b
68a
68b
69a
69b
No.
65
66
70
71
72
CYC
Parameter
LCLK to LA active delay
LCLK to LA float delay
LCLK to LCS2,1 active delay
LCLK to LCS2,1 float delay
LCLK to LBHE active delay
LCLK to LBHE float delay
LCLK to LRD, LWR active delay
LCLK to LRD, LWR float delay
LRDY low to LRD, LWR high delay
LRDY to LRD, LWR hold time
LD to LRD setup time
LD to LRD hold time
LD to LCLK setup time
LD to LCLK hold time
LCLK to LD delay
LCLK to LD float delay
LCLK to LHOLD delay
LHLDA asserted to Read/Write Cycle start
LHLDA minimum pulse width
is the clock period of the PCI clock.
Read/
LHOLD
Write
LHLDA
LCLK
Intel Bus Arbitration Timing
Intel Bus Interface Timing (Master Mode)
70
71
213
72
min.
Limit Values
10
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
1
2
Electrical Characteristics
max.
10
10
10
10
10
10
10
10
10
10
10
PEB 20256 E
PEF 20256 E
Unit
t
t
t
04.2001
C Y C
C Y C
C Y C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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