PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 17
![IC CONTROLLER INTERFACE 388-BGA](/photos/6/98/69826/peb20256e-v21_sml.jpg)
PEB20256E-V21
Manufacturer Part Number
PEB20256E-V21
Description
IC CONTROLLER INTERFACE 388-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PEB20256E-V21.pdf
(232 pages)
Specifications of PEB20256E-V21
Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, PPP, Serial, TMA
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
200mA
Power (watts)
3W
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Circuits
-
Other names
PEB20256E-V21
PEB20256E-V21IN
PEB20256E-V21IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB20256E-V21
Manufacturer:
MAX
Quantity:
63
Company:
Part Number:
PEB20256E-V21
Manufacturer:
Infineon Technologies
Quantity:
10 000
- Current page: 17 of 232
- Download datasheet (3Mb)
List of Tables
Table 1-1
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 6-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Table 9-10
Table 9-11
Table 9-12
Table 9-13
Table 9-14
Table 9-15
Table 9-16
Data Sheet
107
Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Receive Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Transmit Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Example for little/big Endian with BNO = 3 . . . . . . . . . . . . . . . . . . . . . 72
Example for little big Endian with BNO = 7 . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Vector Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Correspondence between PCI memory space and chip select . . . . . 101
C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode) . . . . 104
C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode) . . . 104
C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode) 107
C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode) . .
Channel Specification Registers and Channel Commands . . . . . . . . 115
PCI Configuration Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PCI Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . 127
Threshold Codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Transmit Synchronization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Receive Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Bit Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Bit Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DC Characteristics (Non-PCI Interface Pins) . . . . . . . . . . . . . . . . . . . 204
DC Characteristics (PCI Interface Pins). . . . . . . . . . . . . . . . . . . . . . . 205
PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 207
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . 213
Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Motorola Bus Interface Timing (Master Mode). . . . . . . . . . . . . . . . . . 218
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Transmit Synchronization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Receive Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17
PEB 20256 E
PEF 20256 E
04.2001
Page
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