PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 21

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

1.1
• Configurable port interface which operates in 16-port mode or 28-port mode.
• In 16-port mode protocol processing on up to 16 T1, E1, channelized 4 MBit/s,
• In 28-port mode protocol processing on up to 28 T1, E1 or unchannelized links. T1,
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum
• Concatenation of any, not necessarily consecutive, time slots to logical channels on
• Additional support of unchannelized modes, with data rates of up to 45 Mbit/s on port
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive
• Independently selectable pay load loops for each port
• Provides a test function which allows to switch one out of 16 (28) ports to a test port
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit
• JTAG boundary scan according to IEEE1149.1 (5 pins)
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm, pitch 1.27mm)
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 90 Mbit/s data throughput per direction at 66 MHz
• Estimated power consumption: 3W at 66 MHz
• Also available as device with extended temperature range -40..+85 C
Data Sheet
channelized 8 MBit/s or unchannelized links for frame relay, router or DSLAM
applications with a maximum aggregate data rate of up to 90 Mbit/s per direction at 66
MHz PCI frequency
E1 frame boundaries are indicated by clock gaps
of 16 links, for HDLC, PPP or transparent mode (TMA) processing
each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
zero and 8.192 Mbit/s on all other ports
direction
supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM
interface
address and data bus in Intel mode or Motorola mode) which allows access to the
local bus via the PCI bus or which can communicate with a PCI host processor
through an on-chip mailbox
General Features
21
MUNICH256 Overview
PEB 20256 E
PEF 20256 E
04.2001