PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 30

IC CONTROLLER INTERFACE 388-BGA

PEB20256E-V21

Manufacturer Part Number
PEB20256E-V21
Description
IC CONTROLLER INTERFACE 388-BGA
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB20256E-V21

Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, PPP, Serial, TMA
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
200mA
Power (watts)
3W
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Circuits
-
Other names
PEB20256E-V21
PEB20256E-V21IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB20256E-V21
Manufacturer:
MAX
Quantity:
63
Part Number:
PEB20256E-V21
Manufacturer:
Infineon Technologies
Quantity:
10 000
Data Sheet
AB3
AC6
Pin No.
FRAME
IRDY
Symbol
Output (O)
Input (I)
s/t/s
s/t/s
30
Frame
FRAME indicates the beginning and end
of an access. FRAME is asserted to
indicate a bus transaction is beginning.
While FRAME is asserted, data transfers
continue. When FRAME is deasserted,
the transaction is in the final phase.
When the MUNICH256 is bus master,
FRAME
MUNICH256 i s bus slave, FRAME is an
input. FRAME is tri-stated when the
MUNICH256 is not involved in the current
transaction.
FRAME is updated and sampled on the
rising edge of CLK.
Initiator Ready
IRDY indicates the bus master’s ability to
complete the current data phase of the
transaction. It is used in conjunction with
TRDY. A data phase is completed on any
clock where both IRDY and TRDY are
sampled asserted. During a write, IRDY
indicates that valid data is present on
AD(31:0). During a read, it indicates the
master is prepared to accept data. Wait
cycles are inserted until both IRDY and
TRDY are asserted together.
When the MUNICH256 is bus master,
IRDY is an output. When the MUNICH256
is bus slave, IRDY is an input. IRDY is tri-
stated, when the MUNICH256 is not
involved in the current transaction.
IRDY is updated and sampled on the
rising edge of CLK.
is
an
Function
output.
Pin Description
PEB 20256 E
PEF 20256 E
When
04.2001
the

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