PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 36

• Manufacturer Part Number: PEB20256E-V21
• Description: IC CONTROLLER INTERFACE 388-BGA
• Manufacturer: Infineon Technologies

Specifications of PEB20256E-V21

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, PPP, Serial, TMA
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 200mA
• Power (watts): 3W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 388-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Circuits: -
• Other names: PEB20256E-V21; PEB20256E-V21IN

Data Sheet
AC24
AB24
AA23
Pin No.
LRD
or
LDS
LWR
or
LRDWR
LRDY
or
DTACK
Symbol
Output (O)
Input (I)
I/O
I/O
I/O
I/O
I/O
I/O
36
Read (Intel Bus Mode)
This active low signal selects a read
transaction.
Data strobe (Motorola Bus Mode)
This active low signal indicates that valid
data has to be placed on the data bus
(read cycle) or that valid data has been
placed on the data bus (write cycle).
Write Enable (Intel Bus Mode)
This active low signal selects a write
cycle.
Read
Mode)
This input signal distinguishes write from
read operations.
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. The MUNICH256
asserts LRDY during a read cycle if valid
output data has been placed on the data
bus. In write direction LRDY will be
asserted when input data has been
latched.
In local bus master mode MUNICH256
evaluates LRDY to finish a transaction.
Data Transfer Acknowledge (Motorola
bus mode)
This active low input indicates that a data
transfer may be performed. During a read
cycle data becomes valid at the falling
edge of DTACK. The data is latched
internally and the bus cycle is terminated.
During a write cycle the falling edge of
DTACK marks the latching of data and the
bus cycle is terminated.
Write
Signal
Function
(Motorola
Pin Description
PEB 20256 E
PEF 20256 E
04.2001
Bus