MT90869AG Zarlink, MT90869AG Datasheet - Page 61

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.8.1
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the local frame pulse.
13.9
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072 MHz). For 32 Mb/ s stream
operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072 MHz). The BOAR0 to
BOAR3 registers are configured as follows:
13.9.1
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the backplane frame pulse.
mode, n = 0 to 15 for 32 Mb/s mode)
(where n = 0 to 31 for non-32 Mb/s
Backplane Output Advancement For
2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s
Backplane Output Advancement Registers (BOAR0 - 31)
Local Output Advancement Bits 1-0 (LOA1-LOA0)
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
BOARn Bit
clock Rate 131.072 MHz
15-2
1:0
Table 30 - Backplane Output Advancement (BOAR) Programming Table
0 (Default)
-4 cycles
-6 cycles
-2 cycle
Local Output Advancement
Table 28 - Local Output Advancement (LOAR) Programming Table
Table 29 - Backplane Output Advancement Register (BOAR) Bits
Clock Rate 131.072 MHz
0 (Default)
-4 cycles
-6 cycles
-2 cycle
Reserved
BOA(1:0)
Name
Zarlink Semiconductor Inc.
MT90869
Reset
0
0
Advancement For 32 Mb/s
61
clock Rate 131.072 MHz
Backplane Output
Corresponding Advancement Bits
Reserved
Backplane Output Advancement Register
LOA1
0 (Default)
-1 cycle
-2 cycle
-3 cycle
0
0
1
1
Description
LOA0
0
1
0
1
Advancement Bits
BOA1
Corresponding
0
0
1
1
Data Sheet
BOA0
0
1
0
1