MT90869AG Zarlink, MT90869AG Datasheet - Page 42

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

6.3.1
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The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded
with zeros as shown in Table 7.
The Block Programming Register bit, BPE will be automatically reset LOW within 125us, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by setting the BPE bit of the Block
Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of LBPD2-0 and BBPD2-0 of the Block Programming Register, following a device
reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the
LORS and BORS pin conditions, see Pin Description for further details. The Local Connection Memory shall be
configured to select data from Channel 0 of Backplane input Stream 0 (BSTi0), and the Backplane Connection
Memory shall be configured to select data from Channel 0 of Local input Stream 0 (LSTi0). Alternative conditions
may be established by programming bits LBPD2-0 and BBPD2-0 of the Block Programming Register at the time of
setting Bit BPE to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane
Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
7.0
The MT90869 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each memory has 8,192 locations. See Address Map for Data and Connection
Memory Locations (A14=1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the MT90869 not receiving a master clock, the microprocessor port
shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS to initiate the next access).
BBPD2
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6.
15
15
Microprocessor Port
Memory Block Programming Procedure
BBPD1
LBPD1
14
14
Table 7 - Backplane Connection Memory in Block Programming Mode
Table 6 - Local Connection Memory in Block Programming Mode
LBPD0
BBPD0
13
13
12
0
12
0
11
0
11
0
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