MT90869AG Zarlink, MT90869AG Datasheet - Page 15

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Pin Description
LSTi0-31
C16o
C8o
FP16o
FP8o
LSTo0 - 31
LCSTo0-3
Name
L18, L19, L20, M17,
M18,
M19, M20, N18,
N19, N20, P17, P19,
P20, R18, R19, R20,
T18, T19, T20, U18,
U19, U20, V17, V18,
V19, V20, W18,
W19, Y20, Y17, Y18,
Y19
W13
V13
W14
V14
A17, A18, A19, B18,
B19, B20, C18, C19,
C20, D18, D19, D20,
E17, E18, E19, E20,
F18, F19, F20, G17,
G18, G19, G20,
H18, H19, H20, J17,
J18, J19, J20, K17,
K18
C17, C16, B16, A16
Coordinates
Package
Local Serial Input Streams 0 to 31 (5 V Tolerant with internal pull-down).
These pins accept serial TDM data streams at a data-rate of:-
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o Output Clock (Three-state Output). A 16.384 MHz clock output. The clock
falling edge or rising edge is aligned with the local frame boundary, this is
controlled by the COPOL bit of the Control Register.
C8o Output Clock (Three-state Output). A 8.192 MHz clock output. The clock
falling edge or rising edge is aligned with the local frame boundary, this is
controlled by the COPOL bit of the Control Register.
at the frame boundary. The frame pulse, running at a 8 KHz rate, will be the same
format (ST-BUS or GCI-BUS) as the input frame pulse (FP8i).
Frame Pulse Output (Three-state Output). Frame pulse output is active for
122 ns at the frame boundary. The frame pulse, running at 8 KHz rate, will be the
same style (ST-BUS or GCI-BUS) as the input frame pulse (FP8i).
Local Serial Output Streams 0 to 31 (5 V Tolerant Three-state Outputs). These
pins output serial TDM data streams at a data-rate of:-
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
Refer to descriptions of the LORS and ODE pins for control of the output High or
High-Impedance state.
Local Output Channel High Impedance Control (5 V Tolerant Three-state
Outputs).
Active high output enable which may be used to control external buffering
individually for a set of local output streams on a per channel basis.
LCSTo0 is the output enable for LSTo[0,4,8,12,16,20,24,28],
LCSTo1 is the output enable for LSTo[1,5,9,13,17,21,25,29],
LCSTo2 is the output enable for LSTo[2,6,10,14,18,22,26,30],
LCSTo3 is the output enable for LSTo[3,7,11,15,19,23,27,31].
Refer to descriptions of the LORS and ODE pins for control of the output High or
High-Impedance state.
Frame Pulse Output (Three-state Output). Frame pulse output is active for 61ns
Zarlink Semiconductor Inc.
MT90869
15
Description
Data Sheet