MT90869AG Zarlink, MT90869AG Datasheet - Page 24

no-image

MT90869AG

Manufacturer Part Number
MT90869AG
Description
Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
Manufacturer
Zarlink
Datasheet

Specifications of MT90869AG

Package
272BGA
Number Of Ports
64
Fabric Size
16K x 16K|8K x 8K
Switch Core
Non-Blocking|Blocking
Port Speed
8.192|4.096|2.048 Mbps
Operating Supply Voltage
1.8|3.3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT90869AG
Manufacturer:
ZARLINK
Quantity:
2 388
Part Number:
MT90869AG2
Manufacturer:
ZARLINK
Quantity:
96
By programming the Backplane or Local input channel delay registers, BCDR0-31 and LCDR0-31, users can
assign the Ch0 position to be located at any one of the channel boundaries in a frame. For delays within channel
boundaries, the input bit delay programming can be used.
The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed
anywhere within a frame to a resolution of 1/4 of the bit period.
3.2
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with
greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed
on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4
bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mb/s and 8 Mb/s data rates, respectively.
The local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR31, corresponding to the local
data streams, LSTi0 to LSTi31, and the backplane input delay is defined by the Backplane Input Delay registers,
BIDR0 to BIDR31, which correspond to the backplane data streams, BSTi0 to BSTi31.
BSTi0-31/LSTi0-31
BSTi0-31/LSTi0-31
Channel Delay = 2
Channel Delay = 0
Channel Delay = 1
BSTi0-31LSTi0-31
Input Bit Delay Programming (Backplane and Local Input Streams)
(Default)
FP8i
C8i
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram
3
3
3
2
2
2
1 0
1 0
1 0
7
7
7
6
Channel Delay,1
6
6
Ch 0
5
Ch127
5
Ch126
5
4
4
4
3
3
3
2
2
2
Channel Delay, 2
1 0
1 0
1 0
Zarlink Semiconductor Inc.
7
7
7
6
6
6
MT90869
5
5
5
Ch 1
Ch 0
Ch127
4
4
4
3
3
3
24
2
2
2
1 0
1 0
1 0
7
6
5
Ch0
4
3
6
6
2
5
5
Ch126
Ch125
1 0
4
4
3
3
2
2
1 0
1 0
7
7
7
6
6
6
Ch127
5
Ch126
5
Ch125
5
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
Data Sheet
7 6
7 6
7 6

Related parts for MT90869AG