MT90869AG Zarlink, MT90869AG Datasheet - Page 32

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

The state of the BORS pin is detected and the MT90869 configured accordingly during a RESET operation, e.g.
following power-up. The BORS pin is an asynchronous input and is expected to be hard-wired for a particular
system application, although it may be driven under logic control if preferred.
4.2.1
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the
Backplane Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section
12.4, Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE).
The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also Pin Description)
•
•
•
•
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode).
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0 and is
advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 28, Channel 0, BSTo28_Ch0, is transmitted on BCSTo0 in
advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits for
BSTo29_Ch0, BSTo30_Ch0 and BSTo31_Ch0 are advanced relative to the Frame Boundary by three periods of
C16o, on BCSTo1, BCSTo2 and BCSTo3, respectively.
The BCSTo0-3 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams, BSTo0-31. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 3:
BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, 12, 16, 20, 24 and 28.
BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, 13, 17, 21, 25 and 29.
BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, 14, 18, 22, 26 and 30.
BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, 15, 19, 23, 27 and 31.
(3) With stream BSTo4 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel
Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32,
40 and 48.
(4) With stream BSTo8 operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Period
C16o
2039
2040
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode)
BORS Set LOW, Non-32 Mb/s Mode
1
BCSTo0
0
4
3-1
3-3
Allocated Stream No.
BCSTo1
1
5
BCSTo2 BCSTo3 16 Mb/s
2
6
Zarlink Semiconductor Inc.
MT90869
3
7
32
Ch 0
Ch 0
8 Mb/s
Ch 0
Ch 0
Channel No.
4 Mb/s
Ch 0
Ch 0
2
2 Mb/s
Ch 0
Ch 0
Data Sheet