MT90869AG Zarlink, MT90869AG Datasheet - Page 41

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

6.0
The MT90869 incorporates two connection memories, Local Connection Memory and Backplane Connection
Memory.
6.1
The Local Connection Memory (LCM) is 16-bit wide with 8,192 memory locations to support the Local output port.
The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port
and determines the Backplane-to-Local or Local-to-Local data routing. Bits [14:13] select the control modes of the
Local output streams, namely the per-channel message and the per-channel high impedance output control modes.
In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and channel number as detailed in Table 5.
In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port,
and Section 13.1, Control Register (CR) for details on microprocessor port access.
6.2
The Backplane Connection Memory (BCM) is 16-bit wide with 8,192 memory locations to support the Backplane
output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or
the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bits [14:13] select
the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-channel
high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and
channel number as detailed in Table 5. In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0]
contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port,
and Section 13.1, Control Register (CR) for details on microprocessor port access.
6.3
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power
up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register
(BPR) will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register
and Block Programming Register values, respectively.
Local Connection Memory
Backplane Connection Memory
Connection Memory Block Programming
Connection Memory Description
(Backplane streams only)
Source Stream Bit Rate
Table 5 - Local and Backplane Connection Memory Configuration
16 Mb/s
32 Mb/s
2 Mb/s
4 Mb/s
8 Mb/s
Zarlink Semiconductor Inc.
Source Stream No.
legal values 0:31
legal values 0:31
legal values 0:31
legal values 0:31
legal values 0:15
MT90869
[12:8]
[12:8]
[12:8]
[12:8]
[12:9]
41
Source Channel No.
legal values 0:127
legal values 0:255
legal values 0:511
legal values 0:31
legal values 0:63
[7:0]
[7:0]
[7:0]
[7:0]
[8:0]
Data Sheet