MT90869AG Zarlink, MT90869AG Datasheet - Page 27

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12. For 32 Mb/s streams, the advancement may be
0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7 ns, -15 ns or -22 ns.
4.0
4.1
The input pin, LORS, selects whether the Local output streams, LSTo0-31 are set to high impedance at the output
of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-3 signals. Setting
LORS to a LOW state will configure the output streams, LSTo0-31, to transmit bi-state channel data with per-
channel high-impedance determined by external circuits under the control of the LCSTo0-3 outputs. Setting LORS
to a HIGH state will configure the output streams, LSTo0-31, of the MT90869 to invoke a high-impedance output on
a per-channel basis.
The state of the LORS pin is detected and the MT90869 configured accordingly during a RESET operation, e.g.
following power-up. The LORS pin is asynchronous input and is expected to be hard-wired for a particular system
application, although it may be driven under logic control if preferred.
4.1.1
The data (channel control bit) transmitted by LCSTo0-3 replicates the Local Output Enable Bit (LE) of the Local
Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section 12.3,
Local Connection Memory Bit Definition for setting the Local Output Enable Bit (LE).
The LCSTo0-3 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also Pin Description)
•
•
Bit Advancement = -2
Bit Advancement = -4
Bit Advancement = -6
Bit Advancement = 0
LCSTo0 outputs the channel control bits for streams LSTo0, 4, 8, 12, 16, 20, 24 and 28.
LCSTo1 outputs the channel control bits for streams LSTo1, 5, 9, 13, 17, 21, 25 and 29.
BSTo0-31 /LSTo0-31
BSTo0-31
BSTo0-31 /LSTo0-31
BSTo0-31 /LSTo0-31
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16 Mb/s
Local Port High Impedance Control
Port High Impedance Control
System Clock
LORS Set LOW
131.072 Mhz
/LSTo0-31
(Default)
FP8o
Bit 1
Bit 1
Bit 1
Ch255
Bit 1
Ch255
Bit 0
Ch255
Bit 0
Ch255
Bit 0
Zarlink Semiconductor Inc.
Bit 0
MT90869
Bit 7
27
Bit 7
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
Bit 7
Bit 7
Bit 6
Bit 6
Ch0
Bit 6
Ch0
Bit 6
Ch0
Bit 5
Ch0
Bit 5
Bit 5
Bit 5
Data Sheet
Bit 4
Bit 4