MT90869AG Zarlink, MT90869AG Datasheet - Page 43

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

8.0
8.1
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies
may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
8.2
Upon power up, the MT90869 should be initialized by applying the following sequence:
8.3
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90869. It
is synchronized to the internal clock and remains active for 50 us following release (set HIGH) of the external
RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins LORS
and BORS, the output streams LSTo0- 31 and BSTo0-31 are set to high or high impedance, and all internal
registers and counters are reset to the default state.
The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
When a RESET is applied to the MT90869, the CS line is inhibited and the DTA line may become active through
simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in
applications incorporating multiple devices with individual reset conditions.
9.0
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both ports
there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to
allow either looped back, or uni-directional testing. The transmitter generates a 2
Binary Sequence (PRBS), which may be allocated to a specific stream and a number of channels. This is defined
by a stream number, a start channel number, and the number of consecutive channels following the start channel.
The stream, channel number and the number of consecutive channels following the start channel are similarly
allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 17.
1
2
3
4
5
Power-Up Sequence
Initialization
Reset
Device Power-up, Initialization and Reset
Bit Error Rate Test
Set ODE pin to LOW. This configures the LCSTo0-3 output signals to LOW (i.e. to set optional external
output buffers to high impedance), and sets the LSTo0-31 outputs to high or high impedance, dependent
on the LORS input value, and sets the BCSTo0-3 output signals to LOW (i.e., to set optional external
output buffers to high impedance), and sets the BSTo0-31 outputs to high or high impedance,
dependent on BORS input value. Refer to Pin Description for details of the LORS and BORS pins.
Reset the device by pulsing the RESET pin to zero for at least two cycles of the input clock, C8i.
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 6.3, Connection Memory Block Programming.
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
Zarlink Semiconductor Inc.
MT90869
43
15
-1 or 2
23
-1 Pseudo Random
Data Sheet