MT90869AG Zarlink, MT90869AG Datasheet - Page 16

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Pin Description
ODE
BORS
LORS
NC
IC0
Name
A12
K2
K19
Y12, Y13
A2, A20, B6, B10,
B17, C3, C9, D16,
U2, U3, V2, V3, V11,
V12, V15, V16, W10,
W11, W15, W16,
W17, W20, Y3, Y10,
Y15, Y16
Coordinates
Package
Output Drive Enable (5 V Tolerant, Internal pull-up).
An asynchronous input providing Output Enable control to the BSTo0- 31, LSTo0-
31, BCSTo0-3 and LCSTo0-3 outputs.
When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high
impedance (dependent on the BORS and LORS pin settings respectively) and the
outputs BCSTo0-3 and LCSTo0-3 are driven low.
When HIGH, the outputs BSTo0- 31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are
enabled.
Backplane Output Reset State (5 V Tolerant, Internal pull-down).
When this input is LOW the device will initialize with the BSTo0-31 outputs driven
high, and the BCSTo0-3 outputs driven low. Following initialization, the Backplane
stream outputs are always active and a high impedance state, if required on a per-
channel basis, may be implemented with external buffers controlled by outputs
BCSTo0-3.
When this input is HIGH, the device will initialize with the BSTo0-31 outputs at high
impedance and the BCSTo0-3 outputs driven low. Following initialization, the
Backplane stream outputs may be set active or high impedance using the ODE pin
or on a per-channel basis with the BE bit in Backplane Connection Memory.
Local Output Reset State (5 V Tolerant, Internal pull-down).
When this input is LOW, the device will initialize with the LSTo0-31 outputs driven
high and the LCSTo0-3 outputs driven low. Following initialization, the Local
stream outputs are always active and a high impedance state, if required on a per-
channel basis, may be implemented with external buffers controlled by the
LCSTo0-3.
When this input is HIGH, the device will initialize with the LSTo0-31 outputs at high
impedance and the LCSTo0-3 driven low. Following initialization, the Local stream
outputs may be set active or high impedance using the ODE pin or on a per-
channel basis with the LE bit in Local Connection Memory.
No Connect
No connection to be made.
Internal Connects
These inputs MUST be held LOW.
Zarlink Semiconductor Inc.
MT90869
16
Description
Data Sheet