MT90869AG Zarlink, MT90869AG Datasheet - Page 44

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MT90869AG

Manufacturer Part Number
MT90869AG
Description
Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
Manufacturer
Zarlink
Datasheet

Specifications of MT90869AG

Package
272BGA
Number Of Ports
64
Fabric Size
16K x 16K|8K x 8K
Switch Core
Non-Blocking|Blocking
Port Speed
8.192|4.096|2.048 Mbps
Operating Supply Voltage
1.8|3.3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT90869AG
Manufacturer:
ZARLINK
Quantity:
2 388
Part Number:
MT90869AG2
Manufacturer:
ZARLINK
Quantity:
96
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by
detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. A
counter ’roll-over’ shall occur in the event of an error count in excess of 65535.
The BER operations are controlled by registers as follows (refer to Section 13.3, Bit Error Rate Test Control
Register (BERCR) for overall control, Section 13.10, Local Bit Error Rate (BER) Registers and Section 13.11,
Backplane Bit Error Rate (BER) Registers for register programming details):
The registers listed completely define the transmit stream and channels. When BER transmission is enabled for
these channels, the source bits and the message mode bits, LSRC and LMM in the Local Connection Memory, and
BSRC and BMM in the Backplane Connection Memory, are ignored. The enable bits (LE and BE) of the respective
connection memories should be set to HIGH to enable the outputs for the selected channels.
BER Control Register (BERCR) - Independently enables BER transmission and receive testing for
backplane and local ports.
Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Defines the output stream and start
channel for BER transmission.
Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Defines, for transmit
stream, how many consecutive channels to follow the start channel.
Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel
from where the BER sequence will start to be compared.
Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Defines, for the receive
stream, how many consecutive channels follow the start channel.
Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
stream
FP
Start Ch=254
Length=4
Start Ch=0
Length=256
Start Ch=0
Length=3
FP8i
Channels containing PRBS sequence
Once Started BER transmission continues until stopped by the BER control register:-
Figure 17 - Examples of BER transmission channels
0
0
0
frame boundary
Note: Length = Start Chan. + No. of Consecutive channels
1
1
1
2
2
2
Zarlink Semiconductor Inc.
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3
3
MT90869
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Channels containing data (traffic)
254
254
254
255
255
255
0
0
0
1
1
1
2
2
2
Data Sheet

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