MT90869AG Zarlink, MT90869AG Datasheet - Page 53

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.2
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be instigated at any time within a frame. The BPE bit returns to LOW to indicate the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.
The BPR register is configured as follows.
15-7
6-4
Bit
Block Programming Register (BPR)
BBPD(2:0)
Unused
Name
(a)
(b)
Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
FP8i
FP8i
C8i
C8i
Reset
Figure 19 - Frame Boundary Conditions, GCI - BUS Operation
0
0
Set LOW.
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW.
Zarlink Semiconductor Inc.
MT90869
Frame Boundary
53
Description
Data Sheet
.