MT90869AG Zarlink, MT90869AG Datasheet - Page 54

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.3
Address 0002h.
The BER control register controls backplane and local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
15-12
3-1
Bit
Bit
0
11
10
9
8
7
6
Bit Error Rate Test Control Register (BERCR)
LBPD(2:0)
Reserved
LOCKB
PRSTB
CBERB
SBERRXB
SBERTXB
PRBSB
Name
BPE
Name
Reset
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
RESET
0
0
0
0
0
0
0
0
0
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW.
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 us, upon completion of programming.
Set LOW to abort the programming operation.
Table 17 - Block Programming Register Bits
Reserved.
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
PBER Reset for Backplane.
A LOW to HIGH transition initializes the backplane BER generator to the seed
value.
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the backplane internal bit error
counter and the backplane bit error (BBERR) register to zero.
Start Bit Error Rate Receiver for Backplane.
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the
Backplane Bit error Register (BBCR) on each failure. When set LOW, bit
comparison is disabled and the error count is frozen. The error count is stored
in the Backplane Bit Error Register (BBCR).
Start Bit Error Rate Transmitter for Backplane.
A LOW to HIGH transition starts the BER transmission. When set LOW,
transmission is disabled.
BER Mode Select for Backplane.
When set HIGH, a PRBS sequence of length 2
Backplane port. When set LOW, a PRBS sequence of length 2
for the Backplane port.
Zarlink Semiconductor Inc.
MT90869
54
Description
Description
23
-1 is selected for the
15
-1 is selected
Data Sheet