MT90869AG Zarlink, MT90869AG Datasheet - Page 28

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

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The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented
in LCSTo Allocation of Channel Control Bits to the Output Streams.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and is
advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 28, Channel 0, LSTo28_Ch0, is transmitted on LCSTo0 in
advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits for
LSTo29_Ch0, LSTo30_Ch0 and LSTo31_Ch0 are advanced relative to the Frame Boundary by three periods of
C16o, on LCSTo1, LCSTo2 and LCSTo3, respectively.
The LCSTo0-3 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams, LSTo0-31. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 2:
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus Mode) shows the channel control bits for
LCSTo0, LCSTo1, LCSTo2 and LCSTo3 in one possible scenario which includes stream LSTo0 at a data-rate of
16.384 Mb/s, LSTo1 at 8.192 Mb/s, LSTo6 at 4.096 Mb/s and LSTo7 at 2.048 Mb/s. All remaining streams are
operated at a data-rate of 16.384 Mb/s.
4.1.2
The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams, LSTo0-31. Programming a LOW state will set the stream output of
the MT90869 to High Impedance for the duration of the channel period. See Section 12.3, Local Connection
Memory Bit Definition, for programming details.
The LCSTo0-3 outputs remain active.
LCSTo2 outputs the channel control bits for streams LSTo2, 6, 10, 14, 18, 22, 26 and 30.
LCSTo3 outputs the channel control bits for streams LSTo3, 7, 11, 15, 19, 23, 27 and 31.
(3) With stream LSTo4 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control Bit for
Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
(4) With stream LSTo8 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for Channel 1 will
be transmitted during the C16o clock period nos. 9 and 17.
Period
C16o
2039
2040
2041
2042
LORS Set HIGH
1
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
LCSTo0 LCSTo1 LCSTo2 LCSTo3
0
4
12
8
3-1
3-3
Allocated Stream No.
13
1
5
9
10
14
2
6
Zarlink Semiconductor Inc.
15
11
3
7
MT90869
28
Mb/s
Ch 0
Ch 0
Ch 0
Ch 0
16
8 Mb/s
Channel No.
Ch 0
Ch 0
Ch 0
Ch 0
4 Mb/s 2 Mb/s
Ch 0
Ch 0
Ch 0
Ch 0
2
Ch 0
Ch 0
Ch 0
Ch 0
Data Sheet