MT90869AG Zarlink, MT90869AG Datasheet - Page 3

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Device Overview
The MT90869 has two data ports, the Backplane and the Local port. The Backplane port has two modes of
operation, either 32 input and 32 output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s,
in any combination, or 16 input and 16 output streams operated at 32.768 Mb/s. The Local port has 32 input and 32
output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination.
The MT90869 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
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The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode the contents of the connection memory defines, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for
both the backplane port and the local port. The device will automatically detect whether an ST-BUS or a GCI-BUS
style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period the frame format is determined before switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the local port.
Subrate switching is accomplished by oversampling (i.e., 1 bit switching can be accomplished by sampling a 2 Mb/s
stream at 16 Mbps). Refer to MSAN 175.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the backplane and local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The MT90869 is manufactured in a 27 mm x 27 mm body, 1.27 mm ball-pitch, 272-PBGA to JEDEC standard MS-
034 BAL-2 Iss. A.
Backplane-to-Local, supporting 8 K x 8 K data switching,
Local-to-Backplane, supporting 8 K x 8 K data switching,
Backplane-to-Backplane, supporting 8 K x 8 K data switching.
Local-to-Local, supporting 8 K x 8 K data switching.
Zarlink Semiconductor Inc.
MT90869
3
Data Sheet