SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 70

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
Figure 3-11. Instruction-breakpoint control register.
Figure 3-12. Instruction-breakpoint address-range registers.
Figure 3-13. Data-breakpoint address-range and value-compare registers.
3.9.2
The data-breakpoint address-range and compare-value
registers are shown in
ue of the data breakpoint registers is undefined. (MMIO-
register addresses shown are offset with respect to
MMIO_BASE.)
The data-breakpoint control register is shown in
Figure
(The register address shown is offset with respect to
MMIO_BASE.)
Figure 3-14. Data-breakpoint control register.
3-14
MMIO_BASE
MMIO_BASE
MMIO_BASE
MMIO_BASE
0x10 1000
0x10 103C
0x10 1030
0x10 1034
0x10 1038
0x10 1004
0x10 1008
0x10 1020
offset:
3-14. On RESET, the BDCTL register is cleared.
offset:
offset:
offset:
Data Breakpoints
BICTL (r/w)
BDATAALOW (r/w)
BDATAAHIGH (r/w)
BDATAVAL (r/w)
BDATAMASK (r/w)
BDCTL (r/w)
BINSTLOW (r/w)
BINSTHIGH (r/w)
Figure
PRELIMINARY SPECIFICATION
‘DVC’ Data Value Control:
‘BS’ Break on Store:
‘DC’ Data Control:
0
1
0
1
0
1
2
3
3-13. After RESET, the val-
Breakpoint if data equal
Breakpoint if data not equal
Don’t check data stores
Do check data stores
No checking
Check data addresses
Check data values
Check data value and addresses
31
31
‘IAC’ Instruction address control:
31
31
0
1
Breakpoint if address inside range
Breakpoint if address outside range
27
27
27
27
‘DAC’ Data Address Control:
‘BL’ Break on Load:
23
0
1
0
1
23
23
23
Breakpoint if address inside range
Breakpoint if address outside range
Don’t check data loads
Do check data loads
When the DC bits in the data breakpoint control register
are not set to ‘0’, data breakpoints are activated. When
the value of the DC bits is ‘1’ or ‘3’, any data address from
load operations (if the BL bit is set) and/or store opera-
tions (if the BS bit is set) issued by the DSPCPU is com-
pared against the low and high address-range values.
The DAC bit in the breakpoint control register determines
whether data addresses need to be inside or outside of
the range defined by the low and high address-range
registers. A successful comparison occurs when either:
• DAC = ‘0’ and low ≤ daddr ≤ high, or
• DAC = ‘1’ and daddr < low or daddr > high.
Data Breakpoint Value Mask
19
Data Breakpoint Value
19
Address Range Start
19
Address Range End
19
Address Range Start
Address Range End
15
15
15
15
‘IC’ Instruction control bit:
0 Disable instruction breakpoints
1 Enable instruction breakpoints
11
11
11
11
Philips Semiconductors
7
7
7
7
3
BS BL
3
3
3
DC
IC
0
0
0
0