SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 239

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

Variable Length Decoder
15.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The variable length decoder (VLD) unit Huffman-de-
codes MPEG-1 and MPEG-2 (Main Profile) video bit-
streams[1-3]. This chapter describes a programmers
view of the VLD.
The VLD reads an MPEG stream from SDRAM, decodes
the bitstream under the control of DSPCPU and outputs
two data streams. The output data streams contain mac-
roblock header information and the run-length encoded
DCT coefficients. The output data streams are stored in
the SDRAM buffers.
The VLD unit, operates independently during the slice
decoding process. The remaining decoding of the MPEG
stream is carried out by the DSPCPU.
Figure 15-1. VLD block diagram
HWY_BUS
VLD OVERVIEW
Control
64 Bytes
Interrupt
64 Bytes
MMIO &
CONF REGs
Hdr WR FIFO
Macroblock
Run-Level
WR FIFO
RD Buffer
64 Bytes
ENGINE
DMA
status
status
Control
FLOW
VLD
SHIFTER
escape_codes
15.2
Enabled by the DSPCPU, the VLD unit can be initialized
by hardware or software reset operations. Hardware re-
set is provided by the external TRI_RESET# pin. Soft-
ware reset is provided by one of the VLD commands.
The DSPCPU controls the VLD through the VLD com-
mand register. There are five commands supported by
the VLD:
• Shift the bitstream by some number of bits (a maxi-
• Search for the next start code
• Reset the VLD
• Parse some number of macroblocks
• Flush VLD output buffers to SDRAM
The normal mode of operation will be for the DSPCPU to
request that the VLD to parse some number of macrob-
locks. Once the VLD has begun parsing macroblocks, it
may stop for any one of the following reasons:
PRELIMINARY SPECIFICATION
mum of 15-bit shift)
by Gene Pinkston and Selliah Rathnam
VLD OPERATION
start_code_
detector
mb_addr
mb_type
dct_chr
dctcoef
dctcoef
dmv &
motion
dct_lum
Chapter 15
cbp
(1)
(0)
15-1