SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 186
![IC DIGITAL VIDEO DECODER 100LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
SAA7115HL/V1,518
Manufacturer Part Number
SAA7115HL/V1,518
Description
IC DIGITAL VIDEO DECODER 100LQFP
Manufacturer
NXP Semiconductors
Type
Video Decoderr
Specifications of SAA7115HL/V1,518
Package / Case
100-LQFP
Applications
Set-Top Boxes
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply, Analog
-
Voltage - Supply, Digital
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935270666518
SAA7115HLBE-T
SAA7115HLBE-T
SAA7115HLBE-T
SAA7115HLBE-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7115HL/V1,518
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
- Current page: 186 of 548
- Download datasheet (6Mb)
PNX1300/01/02/11 Data Book
Table 12-6. Memory Configuration Registers
Table 12-7. MM_CONFIG Fields
12.6.2
The PLL_RATIOS register controls the operation of the
separate memory-interface and CPU PLLs. Fields in this
register determine if the PLLs are active and what in-
12-4
Figure 12-2. Memory interface configuration registers.
Figure 12-3. PNX1300 memory and core PLL connections.
MM_CONFIG
PLL_RATIOS
REFRESH Refresh interval in memory clock cycles.
MMIO_base
Field
0x10 0100
0x10 0300
SIZE
Register
offset:
Memory System Clocks
External Clock Input
PLL_RATIOS Register
Default value 1000 (0x03E8).
Memory rank size
TRI_CLKIN
MM_CLK1
MM_CLK0
MM_CONFIG (r/o)
PLL_RATIOS (r/o)
Describes external memory configuration
Controls separate memory and CPU PLLs
(phase-locked loops)
PRELIMINARY SPECIFICATION
Function
Purpose
Memory System
31
31
SD SB CD CB SR
7
0
1
2
3
4
5
6
7
6
PLL
Reserved
512KB
1MB
2MB
4MB
8MB
16MB
32MB
5
4
3
2
CR
0
PLL_RATIOS Register
Table 12-8. PLL_RATIOS Fields
put:output ratio each PLL should generate.
summarizes the field functions.
the PLLs are connected and how fields in the
PLL_RATIOS register control them. For normal opera-
Field
CR
CD
SR
CB
SD
SB
19
CPU:memory ratio
Memory:external ratio
CPU PLL Disable
CPU PLL bypass
SDRAM PLL Disable
SDRAM PLL bypass
DSPCPU PLL
TO DDSes && EVO PLL
SDRAM PLL Bypass
SDRAM PLL Disable
x3, x9
REFRESH
CPU PLL Bypass
16-bit memory interface
CPU PLL Disable
Philips Semiconductors
Function
SDRAM Ratio
5–7 Reserved
0
1
2
3
4
0
1
0
1
0
1
0
1
0
1
Figure 12-3
SB SD CB CD SR
7
1:1
2:1
3:2
4:3
5:4
2:1
3:1
CPU PLL on
CPU PLL off
CPU ← PLL
CPU ← Memory
SDRAM PLL on
SDRAM PLL off
Memory ← PLL
Memory ← external
PNX1300
CPU Ratio
6
PNX1300
Peripheral
Clocks
5
PNX1300
Core
Clock
4
4
BW
3
3
shows how
Table 12-8
2
2
SIZE
CR
0
0
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