SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 209

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

Philips Semiconductors
13.5
Figure 13-3
for three types of read accesses supported by I
EEPROMs. A read from the address currently latched in-
side the EEPROM can be for either a single byte or for
an arbitrary series of sequential bytes. The master
makes the choice by setting the ACK bit after a byte has
been transferred.
Figure 13-3. Protocols supported by the boot block for reading the EEPROM
EEPROM ACCESS PROTOCOLS
Current-Address Read
SDA Line Protocol:
SDA Line Protocol:
SDA Line Protocol:
shows the SDA (serial data) line protocols
Sequential Read
Random Read
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
1 0 1 0
1 0 1 0
Device Address
Device Address
1 0 1 0
Device Address
D
A
0
A
0
Dummy Write
A
0
P
A
0
P
0
P
0
P
A
0
P
0
W
P
0
R
T
E
R
E
A
D
I
R
E
A
D
A
C
K
A
C
K
W
A
C
K
A
D
7
7
2
W
D
A
D
7
6
6
C serial
W
D
A
D
6
5
5
Data n
W
D
D
5
A
4
4
Data n
W
D
D
4
A
3
3
W
D
3
A
2
D
2
W
D
2
A
1
D
1
W
D
A
D
1
0
0
D
A
C
K
A
C
K
0
N
O
A
C
K
S
A
R
D
A random-access read is accomplished by performing a
dummy write, which overwrites the latched address
stored inside the EEPROM. Once the internal address
latch is set to the desired value, one of the other two read
protocols can be used to read one or more bytes.
The boot logic inside PNX1300 uses a single random
read transaction to location 0 of device address 1010000
followed by a sequential read extension to read all re-
quired EEPROM bytes in a single pass.
T
T
7
PRELIMINARY SPECIFICATION
O
D
S
T
P
1 0 1 0
6
Device Address
Data n+1
D
5
D
4
D
3
A
D
0
2
P
D
1
1
P
D
0
0
R
E
A
D
A
C
K
C
D
A
K
7
D
D
7
6
Data n+2
D
D
6
5
D
5
D
4
D
D
4
3
D
D
3
2
D
D
2
1
D
D
1
0
D
C
0
A
K
N
O
C
D
A
K
7
O
S
T
P
D
6
Data n+3
D
5
D
4
D
3
D
2
System Boot
D
1
D
0
N
O
C
A
K
O
S
T
P
13-9