SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 530

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

data cache locking registers
data format
DC/AC Characteristics
DC_LOCK_ADDR
DC_LOCK_CTL
DC_LOCK_SIZE
DC_PARAMS
DC_PARAMS register
dcb 5-6,
dcb operation
DDS 7-3,
debug frontend
debug support
DEST_ADR
device control
device ID
device interrupts
diagnostic mode
dimensions
dinvalid 5-6,
dinvalid operation
direct digital synthesizer 7-3,
dirty bit
dithering
DMA operations
DMA_CTL
downscaling
DPC
Index-4
A B C
dinvalid operation
initialization
LRU replacement
performance evaluation support
rdstatus operation
rdtag operation
planar
description table
register
description table
register
description table
register
description table
fields
picture
PCI interface MMIO register
picture
PCI interface register
audio in unit
algorithm
method
PCI interface
PCI interface MMIO register
picture
5-4
A-21
14-10
8-2
5-3
14-3
1-10
5-3
11-10
11-10
A-22
14-1
5-5
5-5
5-5
14-10
5-6
D
3-7
14-10
3-13
18-3
8-7
3-11
5-8
8-7
5-6
11-2
E
5-6
5-13
5-13
5-13
5-13
5-3
1-12
5-11
5-6
5-6
PRELIMINARY SPECIFICATION
F G
11-3
5-5
8-2
H
11-14
11-14
5-12
I
J
K
L M N O P Q R S T U V W X Y Z
DRAM aperture
DRAM base
DRAM limit
DRAM memory system
DRAM_BASE
DRAM_BASE updates
DRAM_CACHEABLE_LIMIT
DRAM_LIMIT
DSPCPU
DSPCPU operations
dspiabs
dspiadd
dspidualabs
dspidualadd
dspidualmul
dspidualsub
dspimul
dspisub
dspuadd
dspumul
dspuquadaddui
definition
address aperture
address mapping
circuit board design
example block diagrams
example configurations table
features
granularity and sizes
initialization
mode register setting
on-chip interleaving
output driver capacity
power down mode
programming
refresh
signal pins
supported devices
supported rank configurations
description table
PCI interface MMIO register
PCI interface register
picture 5-2,
description table
picture
description table
picture
addressing modes
byte ordering
register model
software compatibility
listed alphabetically
listed by function
A-23
A-29
A-30
A-24
A-31
A-32
5-2
5-5
5-2
12-6
A-25
A-27
A-28
5-2
A-26
12-1
3-3
A-33
5-2
12-5
11-10
12-6
3-2
12-3
3-1
5-13
5-13
5-13
A-2
12-1
12-5
11-10
12-2
12-7
3-4
12-7
12-6
A-1
12-2
12-6
11-7
12-7
3-4
12-9
11-9
12-3
12-2