SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 524

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
bit and the BSX bit in the PCSW register should the
same. This byte sex bit must be set by the software.
Figure C-14
mat as seen in the SDRAM and highway bus. The input
data is byte oriented and no swapping is required in the
VLD unit.
DSPCPU in words, thus the VLD needs to swap the out-
put bytes within a word (shown in
pensate for the CPU swap.
C-8
Figure C-13. Memory image format for audio data
Figure C-15. SSI data format as seen in highway
lsb is the least significant byte
msb is the most significant byte
8-bit data (mono)
in memory
8-bit data (stereo)
in memory
32-bit data
in memory
16-bit data (mono)
in memory
16-bit data (stereo)
in memory
lsb is the least significant byte
msb is the most significant byte
16-bit half-word data
in CPU/MMIOs
describes the VLD input and output data for-
However, the output data is read by the
PRELIMINARY SPECIFICATION
lsb
lsb
lsb
msb
L
R
A+3
A+3
A+3
A+3
A+3
n+3
A+3
n+1
L
R
Figure
D
n+1
n
n
SSI_CTL.EMS = 0
Big Endian Mode
A+2
L
L
A+2
A+2
A+2
A+2
A+2
n+2
n+1
msb
msb
C-14) to com-
lsb
lsb
lsb
msb
A+1
L
A+1
R
A+1
A+1
A+1
A+1
n+1
n
D
and A+3 corresponds to byte-three lane of SDRAM/Hwy
and A+3 corresponds to byte-3 lane of CPU/Hwy
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy
Note: A+0 corresponds to byte-0 lane of CPU/Hwy
L
L
n+1
n
n
A+0
A+0
A+0
A+0
A+0
L
L
A+0
C.4.8
The SSI unit has I/O connections through the external
serial pins and also to the internal 32-bit data highway via
MMIO transactions. The minimum quantity of data to be
analyzed by the CPU is 16-bits (i.e. one half word). The
SSI uses a 16-bit or 1-bit endian-ness; it is detailed in
Section 17.8 on page
in the CPU register is written or read ‘as is’ into/from the
SSI MMIO register. The EMS bit in SSI_CTL determines
which half-word (16-bit) is sent first as pictured in
C-15.
n
n
msb
msb
msb
lsb
Synchronous Serial Interface (SSI)
msb
msb
msb
msb
L
R
A+3
A+3
A+3
A+3
A+3
A+3
n+3
n+1
L
R
D
n+1
n
n+1
Little Endian Mode
SSI_CTL.EMS = 1
17-7. The 32-bit quantity contained
A+2
A+2
A+2
A+2
A+2
L
L
A+2
n+2
n+1
lsb
lsb
Philips Semiconductors
lsb
msb
msb
msb
A+1
A+1
L
R
A+1
A+1
A+1
A+1
n+1
n
L
L
D
n
n
n
A+0
A+0
A+0
A+0
A+0
A+0
L
L
n
n
lsb
lsb
lsb
lsb
Figure