SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 486

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

Philips Semiconductors
Unsigned 16-bit load
pseudo-op for uld16d(0)
SYNTAX
FUNCTION
DESCRIPTION
argument. (Note: pseudo operations cannot be used in assembly source files.)
and writes the result in rdest. If the memory address contained in rsrc1 is not a multiple of 2, the result of
undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xd00, [0xd00] = 0x22,
[0xd01] = 0x11
r30 = 0, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r40 = 1, r20 = 0xd04, [0xd04] = 0x84,
[0xd05] = 0x33
r50 = 0xd01
The
The
The result of an access by
The
[ IF rguard ] uld16 rsrc1 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
temp<7:0> ← mem[rsrc1 + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
uld16
uld16
uld16
bs ← 1
bs ← 0
Initial Values
uld16
operation loads the 16-bit memory value from the address contained in rsrc1, zero extends it to 32 bits,
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
uld16
uld16 r10 → r60
IF r30 uld16 r20 → r70
IF r40 uld16 r20 → r80
uld16 r50 → r90
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r60 ← 0x00002211
no change, since guard is false
r80 ← 0x00008433
r90 undefined (0xd01 is not a multiple of 2)
uld16d ild16 ild16d uld16r
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ild16r uld16x ild16x
uld16d(0)
ATTRIBUTES
SEE ALSO
Result
with the same
uld16
uld16
dmem
197
4, 5
No
—
1
3
A-188
is