SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 357

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
fsignflags
SYNTAX
FUNCTION
DESCRIPTION
stores a bit vector representing the exception flags into rdest. The argument value is in IEEE single-precision floating-
point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If the argument is
denormalized, zero is substituted before computing the sign, and the IFZ bit in the result is set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-59
r30 = 0x40400000 (3.0)
r40 = 0xbf800000 (-1.0)
r50 = 0x80800000 (-1.175494351e-38)
r60 = 0x80400000 (-5.877471754e-39)
r10 = 0, r70 = 0xffffffff (QNaN)
r20 = 1, r70 = 0xffffffff (QNaN)
r80 = 0xff800000 (-INF)
The
The
[ IF rguard ] fsignflags rsrc1 → rdest
if rguard then
fsignflags
fsignflags
rdest ← ieee_flags(sign((float)rsrc1))
31
0
Initial Values
operation computes the IEEE exceptions that would result from computing the sign of rsrc1 and
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
PRELIMINARY SPECIFICATION
fsignflags r30 → r100
fsignflags r40 → r105
fsignflags r50 → r110
fsignflags r60 → r115
IF r10 fsignflags r70 → r116
IF r20 fsignflags r70 → r117
fsignflags r80 → r120
IEEE status flags from floating-point sign
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r100 ← 0
r105 ← 0
r110 ← 0
r115 ← 0x20 (IFZ)
no change, since guard is false
r117 ← 0x10 (INV)
r120 ← 0
OVF
3
Philips Semiconductors
fsign readpcsw
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
fcomp
153
No
—
1
1
3