SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 435

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
mergedual16lsb
SYNTAX
FUNCTION
DESCRIPTION
significant bytes from each 16-bit data rsrc1 and rsrc2 into one 32-bit data in dest register, to convert to quad 8-bit.
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-137
r30 = 0x12345678, r40 = 0xaabbccdd
r10 = 0, r30 = 0x12345678, r40 = 0xaabbccdd
r10 = 1, r30 = 0x01020304, r40 = 0x0a0b0c0d
The arguments rsrc1 and rsrc2 are vectors of two 16-bit data. The mergedual16lsb operation merges the least
The mergedual16lsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
[ IF rguard ] mergedual16lsb rsrc1 rsrc2 → rdest
if rguard then {
}
rsrc1
rdest<31:24> <- rsrc1<23:16>
rdest<23:16> <- rsrc1<7:0>
rdest<15:8> <- rsrc2<23:16>
rdest<7:0> <- rsrc2<7:0>
31
Initial Values
23
PRELIMINARY SPECIFICATION
15
rdest
31
7
mergedual16lsb r30 r40 -> r50
IF r10 mergedual16lsb r30 r40 -> r50
IF r10 mergedual16lsb r30 r40 -> r50
23
0
15
rsrc2
Operation
31
7
Merge dual 16-bit lsb bytes
23
0
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
pack16lsb pack16msb
mergelsb mergemsb
Philips Semiconductors
15
ATTRIBUTES
SEE ALSO
r50 <- 0x3478bbdd
no change, since guard is
false
r50 <- 0x02040b0d
7
Result
shifter
103
1,2
No
0
2
1
-