SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 319

IC DIGITAL VIDEO DECODER 100LQFP

SAA7115HL/V1,518

Manufacturer Part Number
SAA7115HL/V1,518
Description
IC DIGITAL VIDEO DECODER 100LQFP
Manufacturer
NXP Semiconductors
Type
Video Decoderr
Datasheets

Specifications of SAA7115HL/V1,518

Package / Case
100-LQFP
Applications
Set-Top Boxes
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply, Analog
-
Voltage - Supply, Digital
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935270666518
SAA7115HLBE-T
SAA7115HLBE-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAA7115HL/V1,518
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
PNX1300/01/02/11 Data Book
dcb
SYNTAX
FUNCTION
DESCRIPTION
and valid, and the block’s dirty bit is reset. The target block of
addressed by rsrc1 + d. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a
multiple of 4.
operation. If the target block is not dirty or if the block is not in the cache,
taken.
status of data-cache blocks.
causing all non-empty copyback buffers to be emptied to main memory.
operation is carried out or not.If the LSB of rguard is 1, the operation is carried out; otherwise,it is not carried out.
EXAMPLES
A-21
r10 = 0
r20 = 1
The
A valid copy of the target block remains in the cache. Stall cycles are taken as necessary to complete the copy-back
dcb
dcb
The
[ IF rguard ] dcb(d) rsrc1
if rguard then {
}
addr ← rsrc1 + d
if dcache_valid_addr(addr) && dcache_dirty_addr(addr) then {
}
dcb
dcb
dcache_copyback_addr(addr)
dcache_reset_dirty_addr(addr)
has no effect on blocks that are in the non-cacheable SDRAM aperture.
ensures coherency between caches and main memory by discarding all pending prefetch operations and by
operation causes a block in the data cache to be copied back to main memory if the block is marked dirty
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls if the
Initial Values
PRELIMINARY SPECIFICATION
dcb(0) r30
IF r10 dcb(4) r40
IF r20 dcb(8) r50
Operation
dcb
is the block in the data cache that contains the byte
dcb
dcb
has no effect and no stall cycles are
Data cache copy back
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
no change and no stall cycles, since
guard is false
does not change the replacement
Philips Semiconductors
ATTRIBUTES
SEE ALSO
dinvalid
Result
–256..252 by 4
dmemspec
7 bits
205
1
3
5

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