SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 429

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
ld32r
SYNTAX
FUNCTION
DESCRIPTION
result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 4, the result of
undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on
the current setting of the bytesex bit in the PCSW.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
A-131
r10 = 0xcfc, r20 = 0x4,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r50 = 0, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r60 = 1, r40 = 0xd0c, r30 = 0xfffffff8,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r50 = 0xd01, r30 = 0xfffffff8
The
The
The
[ IF rguard ] ld32r rsrc1 rsrc2 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
rdest<7:0> ← mem[rsrc1 + rsrc2 + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + rsrc2 + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + rsrc2 + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + rsrc2 + (0 ⊕ bs)]
ld32r
ld32r
ld32r
bs ← 3
bs ← 0
Initial Values
ld32r
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation loads the 32-bit memory value from the address computed by rsrc1 + rsrc2 and stores the
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
PRELIMINARY SPECIFICATION
ld32r r10 r20 → r80
IF r50 ld32r r40 r30 → r90
IF r60 ld32r r40 r30 → r100
ld32r r70 r30 → r110
Operation
r80 ← 0x84332211
no change, since guard is false
r100 ← 0x48665544
r110 undefined, since 0xd01 +(–8) is not a
multiple of 2
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
32-bit load with index
ld32 ld32d ld32x st32
Philips Semiconductors
st32d h_st32d
ATTRIBUTES
SEE ALSO
Result
ld32r
ld32r
dmem
200
4, 5
No
—
2
3
.
is