SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 339

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
faddflags
SYNTAX
FUNCTION
DESCRIPTION
and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE single-precision
floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEE
exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is
according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before
computing the sum, and the IFZ bit in the result is set. If the sum would be denormalized, the OFZ bit in the result is
set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-41
r10 = 0x7f7fffff (3.402823466e+38),
r20 = 0x3f800000 (1.0)
r30 = 0,
r10 = 0x7f7fffff (3.402823466e+38)
r40 = 1,
r10 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00a00000 (1.469367939e–38),
r81 = 0x80800000 (–1.17549435e–38)
r95 = 0x7f800000 (+INF),
r96 = 0xff800000 (–INF)
r98 = 0x40400000 (3.0),
r99 = 0x00400000 (5.877471754e–39)
The
The
[ IF rguard ] faddflags rsrc1 rsrc2 → rdest
if rguard then
faddflags
faddflags
rdest ← ieee_flags((float)rsrc1 + (float)rsrc2)
31
0
Initial Values
operation computes the IEEE exceptions that would result from computing the sum rsrc1+rsrc2
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
PRELIMINARY SPECIFICATION
faddflags r10 r20 → r60
IF r30 faddflags r10 r10 → r50
IF r40 faddflags r10 r10 → r70
faddflags r80 r81 → r100
faddflags r95 r96 → r105
faddflags r98 r99 → r111
IEEE status flags from floating-point add
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r60 ← 0x2 (INX)
no change, since guard is false
r70 ← 0xa (OVF INX)
r100 ← 0x46 (OFZ UNF INX)
r105 ← 0x10 (INV)
r111 ← 0x20 (IFZ)
fadd fsubflags readpcsw
OVF
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
1, 4
falu
112
No
—
2
3