SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 388

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

Philips Semiconductors
IEEE status flags from convert floating-point to
integer with round toward zero
SYNTAX
FUNCTION
DESCRIPTION
IEEE floating-point value in rsrc1 to a signed integer, and an integer bit vector representing the computed exception
flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.
The exception flags in PCSW are left unchanged by this operation. Rounding toward zero is performed; the IEEE
rounding mode bits in PCSW are ignored. If rsrc1 is denormalized, zero is substituted before computing the
conversion, and the IFZ bit in the result is set.
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
The
The
[ IF rguard ] ifixrzflags rsrc1 → rdest
if rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ifixrzflags
ifixrzflags
31
0
Initial Values
operation computes the IEEE exceptions that would result from converting the single-precision
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
ifixrzflags r30 → r100
ifixrzflags r35 → r102
IF r10 ifixrzflags r40 → r105
IF r20 ifixrzflags r40 → r110
ifixrzflags r45 → r112
ifixrzflags r50 → r115
ifixrzflags r60 → r117
ifixrzflags r70 → r120
ifixrzflags r80 → r122
Operation
PRELIMINARY SPECIFICATION
7
0
OFZ
6
PNX1300/01/02/11 DSPCPU Operations
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r100 ← 0
r102 ← 0x02 (INX)
no change, since guard is false
r110 ← 0x10 (INV)
r112 ← 0x10 (INV)
r115 ← 0x02 (INX)
r117 ← 0x20 (IFZ)
r120 ← 0x10 (INV)
r122 ← 0x10 (INV)
OVF
3
ifixrz ufixrzflags
ifixieeeflags
ufixieeeflags
UNF
ATTRIBUTES
2
SEE ALSO
ifixrzflags
Result
INX
1
DBZ
0
falu
129
1, 4
No
—
1
3
A-90