SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 479

• Manufacturer Part Number: SAA7115HL/V1,518
• Description: IC DIGITAL VIDEO DECODER 100LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7115HL/V1,518

• Package / Case: 100-LQFP
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935270666518; SAA7115HLBE-T; SAA7115HLBE-T

PNX1300/01/02/11 Data Book
ufloatrz
SYNTAX
FUNCTION
DESCRIPTION
format and writes the result into rdest. Rounding is performed toward zero; the IEEE rounding mode bits in PCSW are
ignored. This is the preferred rounding mode for ANSI C. If
the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as
a side-effect of any floating-point operation but can only be reset by an explicit
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates
ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
A-181
r30 = 3
r40 = 0xffffffff (4294967295)
r10 = 0, r50 = 0xfffffffd
r20 = 1, r50 = 0xfffffffd
r60 = 0x7fffffff (2147483647)
r70 = 0x80000000 (2147483648)
r80 = 0x7ffffff1 (2147483633)
The
The
The
[ IF rguard ] ufloatrz rsrc1 → rdest
if rguard then {
}
rdest ← (float) ((unsigned long)rsrc1)
ufloatrzflags
ufloatrz
ufloatrz
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation converts the unsigned integer value in rsrc1 to single-precision IEEE floating-point
PRELIMINARY SPECIFICATION
operation computes the exception flags that would result from an individual
ufloatrz r30 → r100
ufloatrz r40 → r105
IF r10 ufloatrz r50 → r110
IF r20 ufloatrz r50 → r115
ufloatrz r60 → r117
ufloatrz r70 → r120
ufloatrz r80 → r122
Convert unsigned integer to floating-point with
Operation
ufloatrz
r100 ← 0x40400000 (3.0)
r105 ← 0x4f7fffff (4.294967040e+9), INX flag set
no change, since guard is false
r115 ← 0x4f7fffff (4.294967040e+9), INX flag set
r117 ← 0x4effffff (2.147483520e+9), INX flag set
r120 ← 0x4f000000 (2.147483648e+9)
r122 ← 0x4effffff (2.147483520e+9), INX flag set
causes an IEEE exception, such as inexact,
writepcsw
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
rounding toward zero
ifloatrz ifloat ufloat
ifixieee ufloatflags
Philips Semiconductors
Result
ATTRIBUTES
operation. The update of
SEE ALSO
ufloatrz
1, 4
falu
119
No
—
1
3
.