Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 75

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 29. System Exception Register High (SYSEXCPH)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
Interrupt Assertion
System Exception Status Registers
Note:
Description
SPOVF – Stack Pointer Overflow
If this bit is 1, a stack pointer overflow exception occurred. Writing a 1 to this bit clears it to 0.
PCOVF – Program Counter Overflow
If this bit is 1, a program counter overflow exception occurred. Writing a 1 to this bit clears it to
0.
DIV0 – Divide by Zero
If this bit is 1, a divide operation was executed where the denominator was zero. Writing a 1 to
this bit clear it to 0.
SPOVF
R/W1C
7
0
exceptions occur while servicing an exception. When this happens the processor again
vectors to the system exception vector and sets the associated exception status bit. The ser-
vice routine would then have to respond to the new exception.
Upon illegal instruction, the program counter and flags are pushed onto the stack only
once. If the associated exception bit is not reset, the program counter and flags are not
pushed a second time.
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the CPU, the corresponding bit
in the Interrupt Request Register is cleared until the next interrupt occurs. Writing 1 to the
corresponding bit in the Interrupt Request Register clears the interrupt request.
Program code generates interrupts directly. Writing a 1 to the appropriate bit in the Inter-
rupt Request Set Register triggers an interrupt (assuming that interrupts are enabled).
When the interrupt request is acknowledged by the CPU, the bit in the Interrupt Request
Register is automatically cleared to 0.
When a System Exception occurs the system exception status registers is read to deter-
mine which system exception occurred. These registers are read individually or read as a
16-bit quantity.
PCOVF
R/W1C
6
0
R/W1C
DIV0
5
0
P R E L I M I N A R Y
DIVOVF
R/W1C
4
0
FF_E020H
R/W1C
ILL
Z16FMC Series Motor Control MCUs
3
0
R/W1C
2
0
Product Specification
Reserved
R/W1C
Interrupt Controller
1
0
R/W1C
0
0
53