Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 224

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 106. I2CSTATE_H (Continued)
Table 107. I2CSTATE_L
PS028702-1210
State Encoding
1110
1111
State
I2CSTATE_H
0000–0100
0110–0111
0101
1000–1111
I
2
C
Mode Register
The I
ing mode, slave address and diagnostic modes.
Sub-State
I2CSTATE_L
0000
0000
0000
0001
0111
0110
0101
0100
0011
0010
0001
0000
1000
State Name
Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)
Master Transmit Addr2 Master sending second address byte (10-bit addressing)
2
C Mode Register (see Table 108) provides control over Master versus Slave operat-
Master Start
Master Restart
send/receive bit 7
send/receive bit 6
send/receive bit 5
send/receive bit 4
send/receive bit 3
send/receive bit 2
send/receive bit 1
send/receive bit 0
send/receive
Acknowledge
Sub-State Name
–
–
P R E L I M I N A R Y
State Description
Nine substates, one for each address bit and one for the
acknowledge.
Nine substates, one for each address bit and one for the
acknowledge.
State Description
There are no substates for these I2CSTATE_H val-
ues.
There are no substates for these I2CSTATE_H val-
ues.
Initiating a new transaction.
Master is ending one transaction and starting a
new one without letting the bus go non-active.
Sending/Receiving most significant bit.
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
Z16FMC Series Motor Control MCUs
I2C Master/Slave Controller
Product Specification
202