Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 55

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Stop Mode Recovery
PS028702-1210
External Pin Reset
External Reset Indicator
User Reset
Fault Detect Logic Reset
The input-only RESET pin has a schmitt-triggered input, an internal pull-up, an analog fil-
ter and a digital filter to reject noise. After the RESET pin is asserted for at least four sys-
tem clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the Z16FMC device continues to be held in the Reset
state. If the RESET pin is held Low beyond the System Reset timeout, the device exits the
Reset state 16 system clock cycles following RESET pin deassertion. If the RESET pin is
released before the System Reset timeout, the RESET pin is driven Low by the chip until
the completion of the timeout as described in the next section. In STOP mode, the digital
filter is bypassed as the system clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
the Reset Status and Control Register (see page 35)
During System Reset, the RESET pin functions as an open drain (active Low) RESET
mode indicator in addition to the input functionality. This Reset output feature allows a
Z16FMC device to Reset other components to which it is connected, even if the Reset is
caused by internal sources such as POR, VBO, or WDT events and as an indication of
when the reset sequence completes.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in
A System Reset is initiated by setting RSTSCR[0]. If the Write was caused by the OCD,
the OCD is not Reset.
Fault detect circuitry exists to detect Illegal state changes which is caused by transient
power or electrostatic discharge events. When such a fault is detected, a system reset is
forced. Following the system reset, the
ter (see page 35)
STOP mode is entered by execution of a
mation about STOP mode, see the
Table 6 on page 29
is set.
P R E L I M I N A R Y
has elapsed.
Low-Power Modes
FLTD
STOP
bit in the
instruction by the CPU. For detailed infor-
Z16FMC Series Motor Control MCUs
is set to 1.
the Reset Status and Control Regis-
chapter on page 36. During Stop
Reset and Stop Mode Recovery
Product Specification
33