Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 211

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Figure 40. Data Transfer Format – Slave Transmit Transaction with 7-bit Address
Slave Transmit Transaction with 7-bit Address
The data transfer format for a Master reading data from a Slave in 7-bit address mode is
shown in Figure 40. The following procedure describes the I
operating as a Slave in 7-bit addressing mode, transmitting data to the bus Master.
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
2. The Master initiates a transfer, sending the address byte. The SLAVE mode I
3. Software responds to the interrupt by reading the I2CISTAT Register, clearing the
4. SCL is released and the first data byte is shifted out.
5. When the first bit of the first data byte is transferred, the I
6. Software responds to the transmit data interrupt (
7. When the Master receives the data byte, the Master transmits an Acknowledge
8. The bus cycles through steps 5–7 until the final byte has been transferred. If software
Address
follows.
a. Initialize the MODE field in the I
b. Optionally set the
c. Initialize the
d. Set
e. Program the Baud Rate High and Low Byte registers for the I
Controller finds an address match and detects the R/W bit = 1 (read by Master from
Slave). The I
transaction.The
RD
bit. When
Register. Software sets the
interrupts. When the Master initiates the data transfer, the I
Low until software has written the first data byte to the I2CDATA Register.
bit, which asserts the transmit data interrupt.
byte into the I2CDATA Register, which clears
instruction (or Not Acknowledge instruction for the final data byte).
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
Slave
bit is set = 1, indicating a read from the Slave.
mode or MASTER/SLAVE mode with 7-bit addressing.
IEN
RD
= 1 in the I
2
= 1, software responds by loading the first data byte into the I2CDATA
C Controller acknowledges, indicating that it is ready to accept the
SAM
SLA
R=1
bit in the I2CISTAT Register is set = 1, causing an interrupt. The
[6:0] bits in the I
GCE
P R E L I M I N A R Y
2
C Control Register. Set
bit.
TXI
A
bit in the I2CCTL Register to enable transmit
2
2
Data
C Mode Register for either SLAVE-ONLY
C Slave Address Register.
Z16FMC Series Motor Control MCUs
TDRE
NAK
TDRE
A
.
= 0 in the I
= 1) by loading the next data
2
C Master/Slave Controller
2
I2C Master/Slave Controller
C controller sets the
2
C Controller holds SCL
Product Specification
Data
2
C Control Register.
2
C baud rate.
A
2
C
P/S
TDRE
SAM
189