Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 199

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Software Control of I
Master Transactions
The I
MODE[1:0]
ter/Slave or Slave only mode and configures the slave for 7-bit or 10-bit addressing recog-
nition. The baud rate High and Low Byte Registers must be programmed for the I
rate in slave mode as well as in master mode. In slave mode, the baud rate value pro-
grammed must match the master's baud rate within +/- 25% for proper operation.
MASTER/SLAVE mode is used for:
•
•
•
In Slave-only mode the
initiate a master transaction by accident). This restricts the operation to slave only mode
and prevents accidental operation in master mode.
Software controls I
controller or by polling the I
To use interrupts, the I
lowed by executing an
to enable transmit interrupts. An I
Register to determine the cause of the interrupt.
To control transactions by polling, the interrupt bits (TDRE, RDRF, SAM, ARBLST,
SPRS and NCKI) in the I
less of the state of the TXI bit.
The following sections describe the Master read and write transactions to both 7- and 
10-bit Slaves.
Master Arbitration
If a Master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a Slave. If a Master
loses arbitration during a transmit data byte, it releases the SDA line and waits for the next
STOP or START condition.
The Master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit time. This loss occurs if more than one Master is simultaneously
accessing the bus. Loss of arbitration occurs during the address phase (two or more Mas-
Master only operation in a single master, one or more slave I
Master/Slave in a multi-master, multi-slave I
Slave only operation in an I
2
C Controller is configured using the I
field of the I
2
C transactions by enabling the I
2
C Transactions
2
EI
C interrupt must be enabled in the Interrupt Controller and fol-
START
2
2
C Mode Register allows configuring the I
instruction. The TXI bit in the I
C Status Register must be polled. The
P R E L I M I N A R Y
2
C Status Register.
bit of the I
2
C system
2
C interrupt service routine then verifies the I
2
C Control Register is ignored (software cannot
2
C Control and I
Z16FMC Series Motor Control MCUs
2
C system
2
C Controller interrupt in the interrupt
2
C Control Register must be set
2
C Mode registers. The
I2C Master/Slave Controller
Product Specification
2
TDRE
C system
2
C Controller for Mas-
bit asserts regard-
2
C Status
2
C baud
177