Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 216

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Note:
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Slave Read Transaction with Data DMA
In this transaction the I
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If the master sends a Not Acknowledge prior to the final byte, software responds to the
Not Acknowledge interrupt by clearing the
Configure the selected DMA channel for I
DMACTL register for the final buffer to be transferred. Typically one buffer will be de-
fined with a transfer length of N where N bytes are expected to be received from the
master. The watermark is set to 1 by writing a 0x01 to DMAxLAR[23:16].
The I
error conditions.
The I
Slave mode transactions. The
When the SAM interrupt occurs, set the
The DMA transfers the data to memory as it is received from the master.
When the first DMA interrupt occurs indicating that the (N–1)st byte is received, the
NAK
When the second DMA interrupt occurs, it indicates that the Nth byte is received. A
Stop I
the STOP (or RESTART) condition.
Clear the
Configure the selected DMA channel for I
DMACTL register for the final buffer to be transferred. Typically a single buffer with
a transfer length of N is defined.
The I
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I
Slave mode transactions. The
When the SAM interrupt occurs, set the
The DMA transfers the data to be transmitted to the master.
When the DMA interrupt occurs, the final byte is being transferred to the master. The
master must send a Not Acknowledge for this final byte, setting the
I2CSTAT register and generating the I
bit set in I2CSTAT register) follows.
Clear the
bit must be set in the I2CCTL register.
2
2
2
2
2
C interrupt must be enabled in the interrupt controller to alert software of any I
C interrupt must be enabled in the interrupt controller to alert software of any I
C Master/Slave must be configured as defined in the sections above describing
C Master/Slave must be configured as defined in the sections above describing
C interrupt occurs (
DMAIF
DMAIF
bit in the I2CMODE register.
bit in the I2CMODE register.
2
C Master/Slave operates as a slave, sending data to the master.
P R E L I M I N A R Y
SPRS
TXI
TXI
bit set in the I2CSTAT register) when the master issues
bit in the I2CCTL register must be cleared.
bit in the I2CCTL register must be cleared.
2
C interrupt. A Stop or Restart interrupt (
DMAIF
DMAIF
DMAIF
2
2
C transmit. The
Z16FMC Series Motor Control MCUs
C receive. The
bit.
bit in the I2CMODE register.
bit in the I2CMODE register.
I2C Master/Slave Controller
IEOB
IEOB
Product Specification
bit must be set in the
bit must be set in the
NCKI
bit in the
SPRS
2
2
C
C
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