Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 138
Z16FMC64AG20EG
Manufacturer Part Number
Z16FMC64AG20EG
Description
Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC64AG20EG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
- 40 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC64AG20EG
Manufacturer:
Zilog
Quantity:
160
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PS028702-1210
1
0
Idle State
of Line
Figure 18. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the
MULTIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide
MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the LIN-UART address compare register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the LIN-UART processes only frames
addressed to it. You can determine whether a frame of data is addressed to the LIN-UART
is made in hardware, software or a combination of the two, depending on the multiproces-
sor configuration bits. In general, the address compare feature reduces the load on the
CPU because it does not need to access the LIN-UART when it receives data directed to
other devices on the multi-node network. The following 3 MULTIPROCESSOR modes
are available in the hardware:
1. Interrupt on all address bytes.
2. Interrupt on matched address bytes and correctly framed data bytes.
3. Interrupt only on correctly framed data bytes.
These modes are selected with MPMD[1:0] in the LIN-UART Control 1 register. For all
MULTIPROCESSOR modes, bit MPEN of the LIN-UART Control 1 register must be set
to 1.
The first scheme is enabled by writing
address bytes cause an interrupt, while data bytes never cause an interrupt. The ISR checks
the address byte which triggered the interrupt. If it matches the LIN-UART address, the
software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The
software determines the end of the frame and checks for it by reading the MPRX bit of the
LIN-UART Status 1 register for each incoming byte. If MPRX
If the address of this new frame is different from the LIN-UART’s address, then
MPMD[0] must be set to 1 by software, causing the LIN-UART interrupts to go inactive
Start
Bit0
lsb
Bit1
Bit2
P R E L I M I N A R Y
Bit3
Data Field
Bit4
01b
Parity
to MPMD[1:0]. In this mode, all incoming
Bit5
Z16FMC Series Motor Control MCUs
bit location (9th bit) becomes the
Bit6
msb
Bit7
=1
Product Specification
, a new frame has begun.
MP
1
Stop Bit(s)
2
LIN-UART
116
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