Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 205

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Slave Address
1st Byte
Figure 37. Data Transfer Format – Master Read Transaction with 10-Bit Address
9. The I
10. Software responds by reading the I
11. The I
12. If there are more bytes to transfer, the I
13. A NAK interrupt (
14. Software responds by setting the STOP bit of the I
15. A STOP condition is sent to the I
Master Read Transaction with a 10-Bit Address
Figure 37 displays the read transaction format for a 10-bit addressed Slave.
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Follow the procedure below to perform a data transfer for a read operation to a 10-bit
addressed Slave.
1. Software initializes the MODE field in the I
2. Software writes
3. Software asserts the
4. The I
5. The I
6. When the first bit is shifted out, a Transmit interrupt asserts.
7. Software responds by writing the least significant eight bits of address to the I
8. The I
final byte, software must set the
otherwise it sends an Acknowledge.
with 7-bit or 10-bit addressing (I
The MODE field selects the address width for this node when addressed as a Slave,
not for the remote Slave. Software asserts the IEN bit in the I
(write) to the I
Register.
Register.
W=0 A Slave Address
2
2
2
2
2
C Controller asserts the Receive interrupt.
C Controller sends a Not Acknowledge to the I
C Controller sends the Start condition.
C Controller loads the I
C Controller completes shifting of the first address byte.
2nd Byte
2
C Data Register.
11110B
NCKI
START
P R E L I M I N A R Y
bit in I2CISTAT) is generated by the I
followed by the two most significant address bits and a 0
A S Slave Address
bit of the I
2
C Shift Register with the contents of the I
NAK
2
2
C bus protocol allows mixing slave address types).
C Slave.
2
C Data Register. If the next data byte is to be the
1st Byte
bit of the I
2
2
C Control Register.
C Controller returns to step 7.
Z16FMC Series Motor Control MCUs
2
C Mode Register for Master/Slave mode
11110XX
2
C Control Register.
2
R=1
C Control Register.
2
C Slave if it is the final byte;
. The two bits
A
I2C Master/Slave Controller
Product Specification
Data
2
2
C Control Register.
C Controller.
A
XX
Data
2
C Data
are the two
2
C Data
A P
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