Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 220

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

.
:
Table 102. I
PS028702-1210
Bits
2
1
0
Bits
Field
RESET
R/W
ADDR
I
2
C Baud Rate High and Low Byte Registers
Note:
Description (Continued)
NAK – Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH – Flush Data
Setting this bit clears the I
of the I
written to the I
FILTEN – I
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This function
provides the spike suppression filter required in I
pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock
cycle latency on the inputs.
2
C Baud Rate High Byte Register (I2CBRH)
I2C Baud Rate (bps)
7
The I
form a 16-bit reload value,
High and Low Byte Registers must be programmed for the I
well as in master mode. In slave mode, the baud rate value programmed must match the
master's baud rate within +/- 25% for proper operation.
The I
If
2
BRG
C Data Register when an NAK condition is received after the next data byte has been
2
2
2
C Baud Rate High and Low Byte registers (see Tables 102 and 103) combine to
C baud rate is calculated using the below equation.
C Signal Filter Enable
=
0000H
2
C Data Register. Reading this bit always returns 0.
6
, use
2
10000H
C Data Register and sets the TDRE bit to 1. This bit allows flushing
5
=
P R E L I M I N A R Y
BRG
System Clock Frequency (Hz)
--------------------------------------------------------------------------- -
in the equation.
[15:0], for the I
4
FF_E243H
4

BRH
FFH
R/W
BRG[15:0]
2
C Fast Mode. These filters reject any input
2
Z16FMC Series Motor Control MCUs
3
C Baud Rate Generator. The baud rate
2
2
C baud rate in slave mode as
I2C Master/Slave Controller
Product Specification
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0
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