Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 325

Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D

Z16FMC64AG20EG

Manufacturer Part Number
Z16FMC64AG20EG
Description
Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet

Specifications of Z16FMC64AG20EG

Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
- 40 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16FMC64AG20EG
Manufacturer:
Zilog
Quantity:
160
Part Number:
Z16FMC64AG20EG
Manufacturer:
Zilog
Quantity:
10 000
Table 178. GPIO Port Input Timing
PS028702-1210
Parameter
T
SMR
General Purpose I/O Port Input Data Sample Timing
On-Chip Debugger Timing
Abbreviation
GPIO Port Pin Pulse Width to ensure Stop Mode Recovery (for GPIO
Port Pins enabled as SMR sources)
Figure 64 displays timing of the GPIO port input sampling. The input value on a GPIO
port pin is sampled on the rising edge of the system clock. The port value is then available
to the CPU on the second rising clock edge following the change of the port value.
Table 178 lists the GPIO port input timing.
Table 179 provide timing information for the DBG pin. The DBG pin timing specifica-
tions assume a 4 s maximum rise and fall time.
Table 179. On-Chip Debugger Timing
Parameter
DBG
Port Input Data
Register Latch
Input Value
Port Pin
System
Clock
Abbreviation
Figure 64. Port Input Sample Timing
P R E L I M I N A R Y
0 Value May Be Read
TCLK
From Port Input
Data Register
Changes to 0
Port Value
Min
Z16FMC Series Motor Control MCUs
Delay (ns)
System Clock/4
Max
Product Specification
Electrical Characteristics
Min
1 µs
Delay (ns)
Max
303

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