Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 244

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
222
DMA Control Bit Definitions
The following paragraphs explain the control bits of each DMA channel.
DMAxEN
This bit if set by the CPU enables the DMA channel for direct operation. Direct operation
uses the addresses and transfer length, which has been directly written to the DMA Chan-
nel by software.
If this bit is set by a descriptor read then linked list mode is enabled. Linked list operation
starts when an address is written to the DMAxLAR. This write causes the DMA to read in
the descriptor control value and addresses and place them in the DMA Channel.
LOOP
If the DMA is in linked list mode and this bit is set to 1, it prevents the DMA from updat-
ing the descriptor when the buffer is closed. This bit is set to allow lists to loop on them-
selves without software intervention.
TXSIZE
The TXSIZE bits sets the width of the transfer.
00 = 8-bit bytes are transferred on each DMA transfer. The destination and source
addresses increment or decrement by one for each transfers if the DSTCTL and/or SRC-
CTL is selected for increment or decrement. The transfer length is decremented by one.
This allows 64 Kbytes to be transferred.
01 = A 16-bit word is transferred on each DMA transfer. The destination and source
addresses increment or decrement by two if the DSTCTL and/or SRCCTL is selected for
increment or decrement. In word mode the transfer length is still decremented by one. This
allows 64 Kwords to be transferred.
10 = A 32-bit quad is transferred on each DMA transfer. The destination and source
addresses increment or decrement by four if the DSTCTL and/or SRCCTL is selected for
increment or decrement. In quad mode, the transfer length is still decremented by one.
This allows 64 Kquads to be transferred.
DSTCTL and SRCCTL Fields
The DSTCTL and SRCCTL fields control the increment or decrement of the source and
destination addresses. The address is set to increment, decrement or not change on each
DMA transfer.
00 = Fixed
01 = Increment
10 = Decrement
11 = Reserved
PS028702-1210
P R E L I M I N A R Y
DMA Controller