Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 140

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
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LIN System Clock Requirements
The LIN master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a slave does not con-
tain autobaud capability, it must include a baud clock which deviates from the masters by
no more than ±1.5%. These accuracy requirements must include effects such as voltage
and temperature drift during operation.
Before sending or receiving messages, the baud reload High/Low registers must be initial-
ized. Unlike standard UART modes, the baud reload High/Low registers must be loaded
with the baud interval rather than 1/16 of the baud interval.
To autobaud with the required accuracy, the LIN slave system clock must be at least 100
times the baud rate.
LIN Mode Initialization and Operation
The LIN protocol mode is selected by setting either the LIN master (
(
register. To access the LIN control register, the mode select (MSEL) field of the LIN-
UART mode select/status register must be
be initialized with TEN = 1, REN = 1, all other bits = 0.
In addition to the LMST, LSLV and ABEN bits in the LIN control register, a LinState[1:0]
field exists that defines the current state of the LIN logic. This field is initially set by the
LSLV
Parity error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE)
bit. The PLE bit indicates that receive data does not match transmit data when the LIN-
UART is transmitting. This applies to both MASTER and SLAVE OPERATING
modes.
The break detect interrupt (
tected by the slave (break condition for at least 11 bit times). Software uses this inter-
rupt to start a timer checking for message frame timeout. The duration of the break is
read in the
The break detect interrupt (
sage has been received if the LIN-UART is in LINSLEEP state.
In LIN SLAVE mode, if the BRG counter overflows while measuring the autobaud pe-
riod (
ed (
10b
The baud reload high and low registers are not updated by hardware if this autobaud
error occurs. The
) and optionally (for LIN slave) the autobaud enable (
OE
, where the slave ignores the current message and waits for the next Break signal.
Start
bit in the Status 0 Register). In this case, software sets the LinState field back to
RxBreakLength[3:0]
bit to beginning of bit 7 of autobaud character) an overrun error is indicat-
OE
bit is also set if a data overrun error occurs.
P R E L I M I N A R Y
BRKD
BRKD
bit in Status0 register) indicates when a wake-up mes-
bit in status0 register) indicates when a Break is de-
field of the Mode Status Register.
010b
Z16FMC Series Motor Control MCUs
. The LIN-UART control0 register must
ABEN
Product Specification
) bits in the LIN control
LMST
) or LIN slave
LIN-UART
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