N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 65

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.1.10
DQ0
DQ1
DQ0
DQ1
C
S
S
C
Figure 18. Read OTP instruction and data-out sequence
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Program, Erase, or Write instructions:
Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program
(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),
Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector
Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Configuration Register
(WRCR), Write Enhanced Configuration Register (WRECR) and Write NV Configuration
Register (WRNVCR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
At the end of the POR sequence the WEL bit is low, so the next modify instruction can be
accepted.
7
32 33 34
0
6
1
High Impedance
Dummy cycles
5
2
Instruction
4
35
3
3
36 37 38 39 40 41 42 43 44 45 46
4
2
5
1
6
0
7
MSB
7
23
8
6
22 21
9 10
5
DATA OUT 1
24-bit address
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
3
28 29 30 31
2
2
1
1
0
47
0
MSB
7
6
5
DATA OUT n
©2010 Micron Technology, Inc. All rights reserved.
4
3
2
1
0
Instructions
MSB
7
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