N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 38

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Volatile and Non Volatile Registers
Note:
6.3.2
6.3.3
Table 6.
6.4
38/150
0
1
15
31
63
Starting Address
clock cycle number, according to
cycles) to optimize the fast read instructions performance.
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
XIP Volatile Configuration bits (VCR bit 3)
The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to
0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2
or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate
the memory in XIP mode without setting it to 0. See
Wrap: VCR bits 1:0
The bits from 1 to 0 allow the Wrap mode to be available for each kind of read instruction
and protocol. A specific setting provides the ability to read the memory from sequentially
(standard) mode to a wrap mode, where the reads can be confined inside the 16, 32, or 64
byte boundary. For Wrap setting options, see
following table shows an example of the sequence of bytes in the 16-byte, 32-byte, and 64-
byte options, according to the starting address.
Sequence of Bytes Read during Wrap Mode
Volatile Enhanced Configuration Register
The Volatile Enhanced Configuration Register (VECR) affects the memory configuration
after every execution of Write Volatile Enhanced Configuration Register (WRVECR)
instruction: this instruction overwrite the memory configuration set during the POR
sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:
enabling of QIO-SPI protocol and DIO-SPI protocol
HOLD (Reset) functionality disabling
To enable the VPP functionality in Quad I/O modify operations
To define output driver strength (3 bit)
Warning:
0-1-2- . . . -15-0-1- . .
1-2- . . . -15-0-1-2- . .
15-0-1-2-3- . . . -15-0-1- . .
31-16-17- . . . -31-16-17- . .
63-48-49- . . . -63-48-49- . .
16-Byte Wrap
WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
Table 4.: Maximum operative frequency by dummy clock
0-1-2- . . . -31-0-1- . .
1-2- . . . -31-0-1-2- . .
15-16-17- . . . -31-0-1- . .
31-0-1-2-3- . . . -31-0-1- . .
63-32-33- . . . -63-32-33- . .
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32-Byte Wrap
Table 5.: Volatile Configuration
Section 16: Ordering
©2010 Micron Technology, Inc. All rights reserved.
0-1-2- . . . -63-0-1- . .
1-2- . . . -63-0-1-2- . .
15-16-17- . . . -63-0-1- . .
31-32-33- . . . -63-0-1- . .
63-0-1- . . . -63-0-1- . .
64-Byte Wrap
information.
N25Q064 - 3 V
Register. The