N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 60

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Instructions
Note:
9.1.5
60/150
DQ0
DQ1
S
C
DQ0
DQ1
S
C
Data to be written to the SFDP area is in definition phase.
If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If only a
portion of the SFDP area is written to, the portion not used is shipped with bytes in erased
state (FFh).
The instruction sequence for RDSFDP has the same structure as that of a Fast Read
instruction. First, the device is selected by driving Chip Select (S) Low. Next, the 8-bit
instruction code (5Ah) and the 24-bit address are shifted in, followed by 8 dummy clock
cycles.
The bytes of SFDP content are shifted out on the Serial Data Output (DQ1) starting from the
specified address. Each bit is shifted out during the falling edge of Serial Clock (C).
The Read SFDP instruction is terminated by driving Chip Select (S) High at any time during
data output.
Figure 13. Read Serial Flash Discovery Instruction and Data-out Sequence
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins
(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed
(FAST_READ) instruction.
0
7
32 33 34
1
6
High Impedance
Dummy cycles
2
5
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
2
5
1
6
0
7
MSB
23
7
8
22 21
9 10
6
24-bit address*
5
DATA OUT 1
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
5
DATA OUT 2
4
©2010 Micron Technology, Inc. All rights reserved.
3
2
1
0
MSB
N25Q064 - 3 V
7